In recent years, the demand for a reduction in power consumption in a semiconductor device (LSI) is increasing more and more. The interior of an LSI is divided into a plurality of circuit parts (circuit blocks), and power consumption of a circuit whose load is lightened is reduced by reducing the operation frequency.
FIG. 1A is a diagram illustrating a schematic configuration of an LSI in which an operation frequency for each circuit part is changed, and FIG. 1B is a diagram illustrating a time chart indicating the operation of the LSI illustrated in FIG. 1A.
As illustrated in FIG. 1A, an LSI 10 has a plurality of circuit blocks including a first circuit block 11A and a second circuit block 11B, and a power management unit (PMU) 12. The PMU 12 supplies a clock “cka” to the first circuit block 11A and a clock “ckb” to the second circuit block 11B. The PMU 12 divides a system clock “clk” to generate an operation clock and changes the clocks “cka” and “ckb” to be supplied to each circuit block in accordance with a clock mode specified in correspondence to the load state of each circuit block. In this manner, the PMU 12 controls each circuit so as to reduce power consumption while maintaining a desired processing speed.
FIG. 1B illustrates an example of the change in the operation state of the first circuit block 11A. For example, the first circuit block 11A operates at an operation frequency of 100 to 400 MHz, and operates at an operation frequency of 400 MHz in the high-load state where a large amount of data is processed within a brief time and operates at an operation frequency of 100 MHz in the low-load state where a small amount of data is processed within a comparatively long time. In other words, the frequency of the clock “cka” to be supplied to the first circuit block 11A is high when the load is high, and low when the load is low. The power consumption of the first circuit block 11A is larger at the time of operation at 400 MHz than that at the time of operation at 100 MHz.
Similarly, the second circuit block 11B operates at an operation frequency of 50 to 200 MHz in accordance with its load.
The LSI illustrated in FIG. 1A and FIG. 1B changes the frequency of the clock to be supplied to each circuit block, however, the power source voltage supplied to each circuit block is fixed (1.2 V in FIG. 1B).
The power consumption of the circuit block changes in accordance with the operation frequency, however, also changes in accordance with the supplied power source voltage. Therefore, a technique in which power is reduced by reducing not only the operation frequency but also the supply voltage positively in accordance with the load state of the circuit block has been adopted in many cases. Such a technique is referred to as the DVFS (Dynamic Voltage and Frequency Scaling) technique.
FIG. 2A is a diagram illustrating a schematic configuration of the LSI to which the DVFS technique is applied. FIG. 2B is a diagram illustrating a time chart indicating an operation of the LSI illustrated in FIG. 2A.
As illustrated in FIG. 2A, the LSI 10 has a plurality of circuit blocks including the first circuit block 11A and the second circuit block 11B, the PMU 12, and a VREF generation circuit 16.
The first circuit block 11A has an LDO (Low Drop Out) regulator 15A. The second circuit block 11B has an LDO regulator 15B. The VREF generation circuit 16 generates a reference potential VREF to be supplied to the LDO regulators 15A and 15B. The PMU 12 supplies the clock “cka” to the first circuit block 11A and also supplies a control signal “ca” of the supply voltage to the LDO regulator 15A. Further, the PMU 12 supplies the clock “ckb” to the second circuit block 11B and also supplies a control signal “cb” of the supply voltage to the LDO regulator 15B. The PMU 12 changes the frequency of the clock to be supplied and the voltage to be supplied in accordance with the load state of each circuit block specified by the DVFS mode from outside and controls each circuit block so as to reduce power consumption while maintaining the desired processing speed.
When the DVFS technique is applied, if the power source voltage is applied to each circuit block from the outside of the LSI, the number of parts other than the LSI increases, resulting in an increase in the cost. Therefore, a mechanism as illustrated in FIG. 2A is generally adopted, in which the LDO regulator is mounted in correspondence to the circuit block inside the LSI 10, and a single external power source is used, and various voltages are generated inside the LSI to supply a desired voltage to each circuit.
FIG. 2B illustrates an example of the change in the operation state of the first circuit block 11A. For example, the first circuit block 11A operates at an operation frequency of 100 to 400 MHz and on a supply voltage of 0.8 V to 1.2 V. The first circuit block 11A operates on a supply voltage of 1.2 V and at an operation frequency of 400 MHz in the high-load state, and operates on a supply voltage of 0.8 V and at an operation frequency of 100 MHz in the low-load state.
Similarly, the second circuit block 11B operates at an operation frequency of 50 to 200 MHz and on a supply voltage of 0.8 V to 1.2 V in accordance with its load.
Consequently, the PMU 12 outputs a control signal of the frequency of the clock to be supplied to each circuit block and the supply voltage in accordance with the DVFS mode indicating the load state of each circuit block specified from outside. Specifically, the PMU 12 supplies the “cka” of 400 MHz when the first circuit block 11A is in the high-load state and also supplies the “ca” to control the LDO regulator 15A so as to set the supply voltage to 1.2 V. Further, the PMU 12 supplies the “cka” of 100 MHz when the first circuit block 11A is in the low-load state and also supplies the “ca” to control the LDO regulator 15A so as to set the supply voltage to 0.8 V. This also applies to the second circuit block 11B.
In FIG. 2B, the broken line indicates a case where the supply voltage is kept at 1.2 V in the low-load state and by changing the supply voltage from 1.2 V to 0.8 V at the time of the low-load state, the power consumption is reduced by 33% compared to the case of 1.2 V.
FIG. 3A to FIG. 3C are diagrams illustrating the changes in the clock frequency and in the supply voltage in accordance with the load of the first circuit block 11A of the LSI, in which only the clock frequency is changed as illustrated in FIG. 1A and FIG. 1B and the DVFS technique is applied.
As illustrated in FIG. 3A, when only the clock frequency is changed as in FIG. 1A and FIG. 1B, the supply voltage is fixed at 1.2 V and the desired minimum clock frequency by which the first circuit block 11A can process its load is allocated for each clock mode as in FIG. 3A. Then, the PMU 12 changes the frequency of the clock to be supplied to the first circuit block 11A in accordance with the clock mode corresponding to the load. Specifically, the PMU 12 changes the clock frequency to 400 MHz when the load is high, to 200 MHz when the load is medium, to 100 MHz when the load is low, and to 0 MHz when there is no load (i.e., the clock is not supplied).
When the DVFS technique is applied, the frequency of the clock to be supplied to the first circuit block 11A is changed in accordance with the DVFS mode corresponding to the load, and also the LDO regulator 15A is controlled to change the supply voltage. Therefore, as illustrated in FIG. 3B, the desired minimum supply voltage value by which the first circuit block 11A can operate at each clock frequency is allocated for each DVFS mode. That is, a combination of the clock frequency and the supply voltage is set for each DVFS mode so that the power can be reduced in total in accordance with the change in the load state of the first circuit block 11A. Specifically, the clock frequency is changed to 400 MHz when the load is high, to 200 MHz when the load is medium, to 100 MHz when the load is low, and to 0 MHz when there is no load (i.e., the clock is not supplied). Then, the supply voltage is changed to 1.2 V when the load is high, to 1.0 V when the load is medium, to 0.8 V when the load is low, and to 0.8 V or less when there is no load.
FIG. 3C is a diagram illustrating control points by the above-mentioned control in the coordinate system in which the horizontal axis represents the clock frequency and the vertical axis represents the supply voltage, wherein black circles indicate the case where only the clock frequency is changed in FIG. 3A, and white circles indicate the case where the DVFS technique in FIG. 3B is applied. A range surrounded by a solid line indicates a range in which the circuit can operate.
In the operable range of the circuit in FIG. 3C, the closer to the boundary line of the lower limit, the smaller the power consumption is. Therefore, in order to reduce the power consumption, it is desirable to control so that the control point becomes closer to the lower limit of the operable range. In the case where the supply voltage is fixed at 1.2 V in FIG. 3A, the control point is close to the lower limit of the operable range when the clock frequency is 400 MHz, however, the control point becomes more distant from the lower limit of the operable range when the clock frequency is 200 MHz and 100 MHz.
In contrast, when the DVFS technique is applied, the supply voltage is 1.0 V when the clock frequency is 200 MHz the supply voltage is 0.8 V when the clock frequency is 100 MHz, and therefore, the control point becomes close to the lower limit of the operable range. In the state where there is no load, the supply voltage is set to 0 V and the clock frequency is set to 0 MHz, i.e., the state is brought about where no clock is supplied. This state is outside the operable range, however, no circuit block operates, and therefore, it does not cause any problem in particular.
As described above, in order to apply the DVFS technique, a mechanism is provided that generates various supply voltage values and supplies them to each circuit block, and the LDO regulators 15A and 15B change the supply voltage value in accordance with the control of the PMU 12.
In recent years, in order to further reduce power, a very low power source voltage, such as about 0.5 V, is applied in place of a high power source voltage, such as 1.2 V, which is applied from outside illustrated in FIG. 2A and FIG. 2B, and an LDO regulator that operates under such conditions is demanded.
FIG. 4A and FIG. 4B are diagrams illustrating circuit examples of the LDO regulator proposed hitherto, also illustrating together circuit blocks to which the power source voltage is supplied from the LDO regulator.
FIG. 4A is a circuit diagram of an analog type LDO regulator 20. For example, the first circuit block 11A in FIG. 2A corresponds to a circuit block 11 and the LDO regulator 15A corresponds to the analog type LDO regulator 20. The analog type LDO regulator 20 is illustrated as being provided outside in correspondence to the circuit block 11, however, it may be provided as a part of the circuit.
The analog type LDO regulator 15A has s supply transistor 21, a differential amplifier 22, and variable resistors 23 and 24. The supply transistor 21 is a PMOS transistor provided between a high-potential side global power source line 25 of a voltage VDD and a local power source line 26 of the circuit block 11, and an output GA of the differential amplifier 22 is applied to the gate thereof. The variable resistors 23 and 24 are connected in series between the local power source line 26 and a low-potential side power source line 27 of a voltage VSS (0 V) and form a variable voltage divider circuit configured to output a divided voltage of a voltage VDDMA of the local power source line 26 and the VSS. The resistance values of the variable resistors 23 and 24 differ in accordance with the DVFS mode. In other words, it is possible for the variable voltage divider circuit to change the resistance ratio in accordance with the DVFS mode. The differential amplifier 22 generates the output GA in accordance with a difference between a divided voltage MONA output from the variable voltage divider circuit and the reference potential VREF output from the VREF generation circuit 16 in FIG. 2A. Reference symbol “C” indicates a capacitor between the VDDMA and the VSS.
The differential amplifier 22 compares the divided voltage of the supply voltage VDDMA to the circuit block 11 and the VSS with the reference potential VREF, and determines whether or not the VDDMA is higher than the desired minimum voltage value (target value) for the circuit block 11 to operate by a potential comparison in an analog manner. Then, in accordance with the comparison result, if the VDDMA is lower than the target value, the output GA is controlled in an analog manner so that the amount of supply current of the supply transistor 21 is increased, and if the VDDMA is higher than the target value, the GA is controlled in an analog manner so that, on the contrary, the amount of supply current is reduced. Therefore, the VDDMA is kept at the target value at all times. The target value differs depending on the DVFS mode, and therefore, as described above, the resistance values of the variable resistors 23 and 24 are changed in accordance with the DVFS mode, and the resistance ratio of the variable voltage divider circuit can be changed. Consequently, it is possible for the LDO regulator 15A to dynamically change the supply voltage in order to keep the target value by changing the VDDMA toward the target value set for each DVFS mode.
The analog type LDO regulator is an LDO regulator widely used at present in the case where the power supply voltage VDD applied from outside is about 1.2 V.
However, in recent year, in order to further reduce power consumption, the power source voltage VDD is reduced to about 0.5 V and the VDDMA becomes about 0.4 V and the VREF is set to 0.25 V. If the VDD falls to as low as 0.5 V, it is difficult to perform gate potential control in an analog manner with precision because a threshold value of the transistor that forms the LDO regulator 15A is 0.4 V to 0.5 V, and therefore, the VDD enters a sub threshold region. The sub threshold region is a region in which the VDD becomes equal to or less than the threshold value.
Then, a digital type LDO regulator is proposed.
FIG. 4B is a circuit diagram of a digital type LDO regulator 30. FIG. 4B also illustrates together circuit blocks to which the power source voltage is supplied by the LDO regulator 30. For example, the first circuit block 11A in FIG. 2A corresponds to the circuit block 11 and the LDO regulator 15A corresponds to the digital type LDO 30. It may also be possible to provide the digital type LDO regulator 30 as part of the circuit block 11.
The basic configuration and operation of the digital type LDO regulator 30 are the same as those of the analog type LDO regulator 20 in FIG. 4A, however, the following points are different.
(1) The supply transistor 21 is formed by a plurality of supply transistors 21A, 21B, 21C, . . . connected in parallel.
(2) The differential amplifier 22 is replaced with a comparator 28 configured to output the comparison result as a digital value of 0 or 1.
(3) A controller 29 is provided that controls the turning on and off of the plurality of the supply transistors 21A, 21B, 21C, . . . in accordance with the output of the comparator 28.
If the VDDMA is lower than the target value, for example, the comparator 28 outputs “0” and the controller 29 performs control so as to increase the amount of supply current by increasing the number of the plurality of the turned-on supply transistors 21A, 21B, 21C, . . . . On the contrary, if the VDDMA is higher than the target value, the comparator 28 outputs “1” and the controller 29 performs control so as to reduce the amount of supply current by decreasing the number of the plurality of the turned-on supply transistors 21A, 21B, 21C, . . . .
By changing the control to the digital control as described above, the LDO regulator becomes to operate on a VDD level at which no erroneous operation of 0 or 1 does not occur, and therefore, the LDO regulator will operate accurately at the VDD lower than that of the analog type LDO regulator.